1. Field of Invention
The present invention relates to a capacitor for semiconductor devices which prevents resistance between a lower electrode and a plug therein from increasing.
2. Discussion of Related Art
There has been a variety of research directed toward increasing the capacitance density of a semiconductor device in order to allow the capacitor to have a specific amount of capacitance even if the cell area becomes smaller as the device is more highly integrated. To obtain a large amount of capacitance, the lower electrode of a capacitor is configured as a three-dimensional structure such as a stacked or trench structure, enlarging the surface area of the dielectric of the capacitor. However, the stacked or trench structured capacitor is fabricated through a complicated process. Thus, there are limitations in increasing the surface area of the dielectric.
To solve this problem, there has been developed a method of enlarging the capacitance in which the dielectric is made of a substance of a high dielectric constant such as Ta2O5, PZT(Pb(ZrTi)O3), PLZT((PbLa)(ZrTi)O3), PNZT(Pb(NbZrTi)O3), PMN(Pb(MgNb)O3), BST((BaSr)TiO3) and the like.
FIG. 1 shows a cross-sectional view of a capacitor according to a related art.
Referring to FIG. 1, an N type impurity region 13 is formed in a semiconductor substrate 11, which serves as source and drain regions of a transistor including a gate (not shown in the drawing). An insulating interlayer 15 is formed on the semiconductor substrate 11 to cover the transistor. And a contact hole 17 (see FIG. 2A) exposing the impurity region 13 is patterned in the insulating interlayer 15.
The contact hole 17 is filled with impurity doped polysilicon to form a plug 19 which is electrically connected with an impurity region 13. Specifically, the plug 19 is formed by depositing the doped polysilicon by chemical vapor deposition (hereinafter abbreviated CVD) and by etching back the doped polysilicon to expose the insulating interlayer by reactive ion etching (hereinafter abbreviated RIE).
A barrier layer 21 and a lower electrode 23 are successively deposited on the insulating interlayer 15 including the plug 19. The barrier layer 21, which is in contact with the plug 19, is made of TiN, TaN or the like. The lower electrode 23 is formed by depositing oxidation-resistant metal such as Pt, Mo, Au or another metal of which the oxide is electrically-conductive such as Ir, Ru and the like on the barrier layer 21. The barrier layer 21 prevents silicide from being formed by the reaction between the metal of the lower electrode 23 and the silicon of the plug 19. This is because silicide is easily oxidized into an insulator.
A dielectric layer 25 is formed on the insulating interlayer 15 to cover the lower electrode 23. The dielectric layer 25 is made of a substance, of which the dielectric constant is high, such as Ta2O5, BST((BaSr)TiO3), PZT(Pb(ZrTi)O3), PLZT((PbLa)(ZrTi)O3), PNZT(Pb(NbZrTi)O3), PMN(Pb(MgNb)O3), etc. An upper electrode 27 is made of the same metal as the lower electrode 23 on the dielectric layer 25. When the lower and upper electrodes 23 and 27 are formed with oxidation-resistant metal, they are prevented from being oxidized even if they come into contact with the dielectric layer 25. Moreover, when they are made of metal of which the oxide is conductive, resistance stops increasing.
FIG. 2A to FIG. 2D show cross-sectional views of fabricating a capacitor according to the related art of FIG. 1.
Referring to FIG. 2A, an insulating interlayer 15 is formed on a P-type semiconductor substrate 11 including an N-type impurity region 13 which serves as source and drain regions of a transistor having a gate (not shown in the drawing). A contact hole 17 exposing the impurity region 13 by patterning the insulating interlayer 15 by photolothography.
Referring to FIG. 2B, impurity doped polysilicon is deposited on the insulating interlayer 15 to fill up the contact hole 17 by CVD. In this case, polysilicon is contacted with the exposed impurity region 13 through the contact hole 17. A plug 19 is formed by etching back the polysilicon to expose the insulating interlayer 15 by RIE. In this case, polysilicon remains only in the contact hole 17.
Referring to FIG. 2C, a barrier layer 21 contacted with the plug 19 is formed by depositing TiN or TaN on the insulating interlayer 15. A lower electrode 23 is formed by depositing oxidation resistant metal such as Pt, Mo, Au, etc. or another metal of which the oxide is electrically conductive such as Ir, Ru or the like on the barrier layer 21. In this case, the barrier layer 21 prevents the lower electrode 21 from being reacted with the plug 19, thereby eliminating the formation of silicide between the barrier layer 21 and the plug 19.
The lower electrode 23 and barrier layer 21 are patterned to remain at the part corresponding to the contact hole 17 by photolithography. In this case, the lower electrode 23 and barrier layer 21 are paterned to have the barrier layer 21 come into contact with the plug 19.
Referring to FIG. 2D, a dielectric layer 25 is formed by depositing a substance, of which dielectric constant is high, such as Ta2O5, BST((BaSr)TiO3), PZT(Pb(ZrTi)O3), PLZT((PbLa)(ZrTi)O3), PNZT(Pb(NbZrTi)O3), PMN(Pb(MgNb)O3) or the like on the insulating interlayer 15 to cover the lower electrode 23. Oxidation of the lower electrode 23 made of an oxidation-resistant substance such as Pt, Mo, Au and the like is prohibited even though the lower electrode 23 is contacted with the dielectric layer 25 which includes oxygen atoms. Moreover, when the lower electrode 23 is made of metal of which the oxide is electrically conductive, resistance stops increasing because of the electric conductivity of metal oxide.
An upper electrode 27 is formed by depositing the same substance of the lower electrode 23 on the dielectric layer 25. In this case, oxidation of the upper electrode 27 made of an oxidation-resistant substance such as Pt, Mo, Au and the like is prohibited even though the upper electrode 27 is contacted with the dielectric layer 25 which includes oxygen atoms, too. Moreover, when the upper electrode 27 is made of metal of which the oxide is electrically conductive, resistance stops increasing because of the electric conductivity of metal oxide as well.
Then, the upper electrode 27 and dielectric layer 25 are patterned to remain on the corresponding part to the lower electrode 23. In this case, a portion of the dielectric layer 25 inserted between the upper and lower electrodes 27 and 23 is used as a charge-storing dielectric.
Thus, electric capacitance of a capacitor according to the related art may be increased by forming the dielectric layer with a substance of a high dielectric constant.
Unfortunately, oxygen contained in the dielectric substance having a high dielectric constant diffuses through the sides of a barrier layer to oxidize the barrier layer, thereby increasing contact resistance between the plug and the lower electrode.
Moreover, it is hard to increase electric capacitance of the capacitor due to the limited surface area of the dielectric layer between the upper and lower electrodes.
Accordingly, the present invention is directed to a capacitor for semiconductor devices and a fabricating method thereof that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
The present invention provides, in part, a capacitor of which electric capacitance is increased by increasing the surface area of a dielectric layer between upper and lower electrodes.
The present invention also provides, in part, a method of fabricating a capacitor which prevents the contact resistance between a plug and a lower electrode from increasing by prohibiting the oxidation of a barrier layer which occurs because of exposure to oxygen through the sides of the barrier layer.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention, in part, provides a capacitor that includes a semiconductor substrate, an insulating interlayer on the semiconductor substrate, the insulating interlayer having an elevated region, wherein a contact hole is formed in the elevated region of the insulating interlayer, a plug filling up the contact hole so as to be in contact with the semiconductor substrate, an adhesive layer on the insulating interlayer and in contact with the plug, a first barrier layer on a top surface of the adhesive layer and a second barrier layer at sides of the elevated region of the adhesive layer, a first lower electrode on the first barrier layer, a second lower electrode at sides of the first and second barrier layers and the insulating interlayer, a dielectric layer on the first and second lower electrodes, and an upper electrode on the dielectric layer.
In another aspect, the present invention, in part, provides a method that includes forming an insulating interlayer on a semiconductor substrate, forming a contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a plug in the contact hole so as to be in contact with the semiconductor substrate, forming an adhesive layer, a first barrier layer and a first lower electrode on the insulating interlayer successively, selectively removing portions of the adhesive layer, the first barrier layer, the first lower electrode and the insulating interlayer such that said adhesive layer, said first barrier layer and said first lower electrode remain on an elevated region of the insulating interlayer around the plug, the elevated region defining exposed sides of the insulating interlayer, forming a second barrier layer at sides of the adhesive layer, forming a second lower electrode at the exposed sides of the insulating interlayer and on the first and second barrier layers, forming a dielectric layer on the first and second lower electrodes, and forming an upper electrode on the dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.